The advent of deep sub-micron technologies poses a number of profound challenges to the designer of advanced digital integrated circuits such as microprocessors, wireless communications, multimedia processors and ASICs. This state-of-the-art course presented by a leading expert in the field identifies the compelling issues facing the designer of the next decade and presents both analysis and solution techniques. Topics include the perspective and impact of technology scaling, high-performance and low-power design, timing and synchronization techniques, signal integrity, interconnect, reconfigurable logic and memory design. Extra focus will be given to the following topics: Low power and low-voltage, process variations and robustness, and memory design in the nanoscale era. This will reflected in both the lectures and the preferred projects.

Prerequisites

An undergraduate or introductory level course on digital integrated circuits is required. UC BERKELEY faculty STRONGLY urge NTU students to take IC 541CA (UCB number EECS 141) It is the official prerequisite for this course for all Berkeley graduate students who are preparing for a career in IC analog design.  Undergraduate level courses on components and design techniques for digital systems and integrated circuit devices would be helpful.

• Fundamentals - Technology and modeling
•    Design Tolerances - scaling bounds
•    Design for deep-submicron devices
•   Impact of interconnect
• Design techniques for HIGH SPEED CMOS:
•    Logic and transistor level optimization
•    Transistor sizing for speed
•    Logic styles - pass-transistor logic, dynamic
•    Signal integrity
• Design techniques for LOW POWER:
•    Analysis of power consumption sources
•    Low voltage design     
•    Constant throughput vs. variable throughput design
•    Power minimization at the circuit level
•    Adiabatic design
• Timing
•    Clocking strategies
•    Timing analyses, clock distribution
•    Clock Skew, design of latches and flip-flops
•    Self-timed design
•    Synchronization and Arbiters
•    Phase-locked loops
• Datapath design:
•    Advanced adder and Multiplier design
•    Driving Interconnect
•    IO design
• Memory design:
•    Evolution and trends
•    Low-power memory design
• Design for Testability

Required: Digital Integrated Circuits: A Design Perspective, Jan Rabaey, Prentice Hall, 2nd edition, 2003, 0130909963.

Disclaimer: Textbook information is provided only to give more information about the course.  Do Not use this information to purchase a textbook.  Up-to-date information will be provided when you register.