Contributing Scholar - Paul Franzon, North Carolina State University

3 Semester Credit Hours

Course Description

Modern digital design practices based on Hardware Description Languages Verilog, VHDL) and CAD tools, particularly logic synthesis. Emphasis on design practice and the underlying algorithms. Introduction to deep submicron design issues, particularly interconnect and low power, and to modern applications, including multimedia, wireless, telecommunications and computing.

Prerequisites

• Upper-division undergraduate course in circuit design.
• An undergraduate course in digital systems such as NEEP 2221.
• General experience with the use of CAD Tools.
• General prerequisite: Students must have the knowledge resulting from completing all coursework in the curriculum for a BS degree in Computer Engineering from an ABET-accredited engineering program in the United States or a CEAB-accredited program in Canada, or the equivalent from a foreign institution; performance level in this coursework should be equivalent to a cumulative undergraduate GPA of 2.9 or better on 4.0 scale.
  

Course Objectives

The objective of this course is to prepare you to be an ASIC or FPGA designer in industry. To this end we will focus on how to execute and capture a large complex design in an HDL, using Verilog as the main example. We will also cover a number of other issues important to ASIC designers, including Verification, Design For Test, low power design, etc. You will demonstrate your ability to design a complex ASIC or FPGA function via a major project.

Course Topics

The following topics will be covered in the order given.

• Introduction to ASIC design
• Timing design
• Introduction to design with Verilog
• Design with Verilog
• How to design complex systems
• Verification
• Design for test
• CMOS and low power