Course Description: This course will provide an overview of issues related to the testing and reliability of VLSI circuits. A wide range of VLSI testability analysis and design methods will be covered to give and prepare the students for the modern industrial and academic environments.

Course Objectives: To enable students to understand how to test VLSI circuits that they design or use.

Course Outline by Topical Areas:

• Logic Simulation (Compiled and Event-Driven Simulation).
• Fault Modeling (Defects vs. Faults, Redundancy, Stuck-at, Bridging, Delay).
• Fault Simulation (Serial, Deductive, Concurrent).
• Combinational Test Generation (Path Sensitization, D-alg, PODEM, FAN).
• Sequential Test Generation (Time-Frame Expansion, Initializability, Reachability).
• Design for Testability (Test Points, Full and Partial Scan).
• Built-In Self Test (Pseudo-Random Pattern Generation, BIST Architectures).
• Embedded care test and FPGh test.

Disclaimer: The course syllabus may differ slightly from this.  Course descriptions will be provided in your online course. Textbook information is provided only to give more information about the course.  Do Not use this information to purchase a textbook.  Up-to-date information will be provided when you register.